This application is based upon and claims priority from prior French Patent Application No. 99-12149, filed Sep. 29, 1999, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention generally relates to memory devices, and more particularly to a column register suitable for an integrated circuit memory for instance in EEPROM technology, of the serial or parallel type, and a method of writing in said memory.
2. Description of the Prior Art
Such a memory contains cells arranged in a matrix of rows and columns. A memory cell memorizes the value of one bit in the memory. The cells of a same column are connected to a same connection line, classically depicted vertically and called bit line. Also, cells of a same row are connected to a same connection line, classically depicted horizontally and called word line.
As shown in FIG. 1, a cell M comprises a floating gate transistor TGF forming a non-volatile memorization element whose drain is connected to the bit line BL via a selection transistor TS, which is an N-type MOS transistor. In operation, the sources of the floating gate transistors of a same line are connected to ground, in general via another selection transistor (not shown) common to several adjacent cells. The gate of the floating gate transistor TGF is connected to a command gate line CG. That of the selection transistor TS is connected to the word line WL.
The erasure and programming of an EEPROM cell are obtained by the tunnel (xe2x80x9cFowler Nordheimxe2x80x9d) effect. To this end, a high programming voltage VPP on the order of 18 volts is generated by any adapted means from the memory""s supply voltage VCC, which is on the order of 5 volts.
An erased cell is a cell in which the floating gate of transistor TGF is negatively charged. In order to erase a cell, it is then necessary to supply it with voltages enabling to xe2x80x9ctrapxe2x80x9d free electrons of the floating gate. Accordingly, it is necessary to apply the voltage VPP on line CG and on line WL, and to apply a zero voltage on line BL or to set that line to a high impedance state. The erased state of a cell corresponds for example to the memorization of a binary data 1.
A programmed cell is a cell in which the floating gate of transistor TGF is positively charged. To program a cell, it is therefore necessary to supply it with voltages capable of xe2x80x9csnatchingxe2x80x9d electrons from the floating gate. Accordingly, it is necessary to apply the voltage VPP on line BL and on line WL, and to apply a zero voltage to line CG. The programmed state of a cell corresponds e.g. to the memorization of a binary data 0.
According to the above example, the writing of any binary value in a cell comprises a step of erasing the cell (so that it memorizes the binary data 1), then, when the binary data to be written is 0, a step of programming the cell. The initial erasure step at the programming step serves to control the charge of the floating gate under all circumstances. The programming step is conditional in the sense that it only takes place if the binary data to be written is 0.
In order to implement the programming step, the memory comprises, for each bit line, a high-voltage memorization and switching latch, or more simply a high-voltage latch. This latch forms part of a register known as a bit line register or a column register. Such a latch has a twofold function. Firstly it serves to memorize a binary data for the purpose of writing in a cell. Secondly, it serves to bring the bit line to which the cell is connected to voltage VPP, if the binary data to be written is 0. This second function of the latch is referred to as conditional switching.
FIG. 2 shows the diagram of a high voltage latch as known in the state of the art.
The latch BHT shown in FIG. 2 first of all comprises high voltage memorization means for provisionally memorizing a binary data 1 or 0, respectively in the form of a high voltage VPP or a zero voltage.
These means classically comprise two inverters I1 and I2 connected xe2x80x9chead-to-tailxe2x80x9d between a node A and a node B so as to produce a memorization effect. They are high voltage inverters in the sense that they can receive and deliver a voltage of either zero or VPP. They are classically CMOS technology inverters, i.e. they comprise a P-type MOS transistor and an N-type MOS transistor in series between the high voltage source VPP and ground, the gates of the two transistors being connected together and the output of the inverter being taken at the node corresponding to the common source of the two transistors. By convention, the output of the memorization means is taken at node B and their input is taken at node A. In other words, the binary data stored by the latch is 0 when node B is brought to the zero potential (ground potential) and is 1 when node B is brought to the high voltage VPP (potential referenced with respect to ground).
The high voltage latch BHT also comprises loading means, for loading a binary data in the high voltage memorization means.
These loading means firstly comprise an N-type transistor designated N1 connected to node A by its drain and to a node R by its source. In operation, the node R is connected to ground via a selection transistor (not shown). The gate of transistor N1 receives a signal DATA bar which is a low voltage signal (i.e. whose level is either zero or equal to VCC) representing the inverse of the binary data to be written. In other words, the level of signal DATA bar is zero if the binary data to be written is 1 and is equal to VCC if the binary data to be written is 0. When its level is equal to VCC, the signal DATA bar serves to bring node B to the VPP voltage, which loads the binary value 1 into the high voltage memorization means I1, I2.
Secondly, the loading means comprise another N-type MOS transistor, designated N2, having its drain connected to node B and its source to node S. In operation, the node R is connected to ground either directly or via another selection transistor (not shown). The gate of transistor N2 is connected to a node T to receive a reset to zero signal RLAT, which is also a low voltage signal. When its level is at VCC, this signal serves to bring node B to ground potential, so loading the binary value 0 into the memorization means I1, I2.
The loading of a binary data in the memorization means I1, I2 is carried out in two stages: at a first stage, the signal RLAT passes to VCC, so connecting node B to ground via the transistor N2 which is conducting, so that a 0 is loaded into the memorization means I1, I2; The signal RLAT then returns to zero to block transistor N2; at a second stage, the inverse of the binary data to write is brought to the gate of transistor N1 by means of the signal DATA bar, so that node A is brought to ground potential via transistor N1 only when the binary data to be written is 0, which then has the effect of loading the binary value 1 into the memorization means I1, I2.
The high voltage latch BHT further comprises conditional switching means to bring or not bring to the voltage VPP the bit line BL to which the cell is connected depending on the value memorized by the high voltage memorization means.
These conditional switching means comprise an N-type MOS transistor designated SW connected by its gate to the output of the high voltage memorization means I1, I2 (i.e. at node B), to the bit line BL by its source and by its drain to the high voltage supply source VPP via an N-type MOS transistor designated WRT. The gate of transistor WRT receives a control signal WRMD which makes it conducting during the memory write operations (i.e. in the write mode) and which blocks it during the memory readout operations (i.e. in the read mode). Transistor WRT thus has the function of isolating the bit line BL from the high voltage VPP in the read mode. In the write mode, transistor SW provides the function of conditionally switching the high voltage latch since it allows to bring the bit line BL to the high voltage VPP only when the binary value memorized in the memorization means I1, I2 is 1, that is when the binary data to write is 0.
In general, at least eight binary data are written simultaneously into the memory. These eight binary data form a data word or a binary word. A memory word designates eight adjacent cells of a same line of the memory memorizing the binary word. A memory word therefore memorizes the value of one byte of the memory. In certain cases, several memory words of a same memory line are written simultaneously, sometimes all the words of that line: this is known as page mode writing. In what follows, the term xe2x80x9cwordxe2x80x9d shall sometimes be used in isolation to designate either a binary word or a memory word, depending on the context.
Writing a binary word in the memory comprises a step of simultaneously erasing all the cells of the memory word (so that they memorize the binary data 1), then a step of conditional programming simultaneously for all the cells of the memory word (so that only the thus programmed cells store the binary value 0).
For writing a data word, eight binary bits are loaded into eight high voltage latches such as the one shown in FIG. 2. Indeed, there is in general one such latch per bit line of the memory, to allow the simultaneous writing into all the cells of a same memory word, or even into all the cells of a same memory line (page mode).
Now, the high voltage latches such as shown in FIG. 2 occupy a lot of space on the doped silicon substrate on which the memory is formed, in particular owing to the size of the transistors that must allow them to withstand strong currents and high voltages. As a result, the column register occupies a considerable area of silicon. For low capacity memories (with few memorized bytes), this area is comparablexe2x80x94or even greaterxe2x80x94than that occupied by the memory storage space. Thus, in FIG. 3 there is shown schematically the area occupied by the memory storage plane MM of one byte comprising eight memory cells M0 to M7 forming a memory word and the area occupied by the corresponding eight high-voltage latches BHT0 to BHT7. It can be appreciated that this area occupied by the high-voltage latches is penalizing in terms of fabrication cost, especially for low capacity memories.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.
According to a preferred embodiment of the present invention, a preferred implementation will remedy the drawbacks of prior art memories as discussed above. In view of the foregoing, a preferred embodiment of the present invention contemplates a column register suitable for an integrated circuit memory, for instance in EEPROM technology, which comprises, for a memory word having 2p memory cells each connected to a respective bit line:
2q high-voltage latches, where q is a whole number less than p, each comprising high-voltage memorization means for memorizing a binary data in the form of a high programming voltage or a zero voltage, coupled to conditional and selective switching means, to bring to the high programming voltage a determined bit line among 2p-q bit lines; and
2p-2q low-voltage latches, each comprising low-voltage memorization means for memorizing a binary data in the form of a low supply voltage or a zero voltage, and coupling means at the input of one of the high-voltage latches, Which can be activated to load into the high-voltage latch the binary data memorized in the low-voltage latch.
In an example which shall be detailed below, p is equal to 3 and q is equal to 2. Thus, for a memory word of eight memory cells, the column register in accordance with the invention comprises four high-voltage latches and four low-voltage latches instead of the eight high-voltage of a register according to the state of the art. Now, a low-voltage latch takes up a lot less space on the doped silicon substrate than a high-voltage latch. The invention therefore makes it possible to reduce the space globally occupied by the column register on the silicon substrate.
The invention also concerns a memory, notably in EEPROM technology, comprising a memory plane with at least one memory word of 2p cells, each connected to a respective bit line, which comprises a column register such as defined above.
Moreover, the invention also proposes a method of writing at least one data word of 2p bits in such a memory, which comprises the following steps:
1) erasing all the cells of the memory word;
2) loading 2q data in the 2q high-voltage latches, and loading 2p-2q other data in the 2p-2q low-voltage latches;
3) programming 2q cells of the memory as a function of the data memorized in the 2q high-voltage latches;
as well as repeating 2p-qxe2x88x921 times the following steps:
4) loading, in the 2q high-voltage latches, of 2q of the other data that were loaded in 2q low-voltage latches at step 2);
5) programming 2q other cells of the memory as a function of the data memorized in the 2q high-voltage latches.